Many ASIC wirebond chips are not IO-limited, meaning the image/package can support more IOs than the design requires. In some designs the internal logic of the design of the IC chip dictates the size and thus more IO cells than are needed are formed in the IO collar surrounding the IC chip. Since IO cells can only occupy the IO sites, the unused IO sites are wasted space. IO cells tend to be very large compared to the other logic and, depending on the number of unused IO sites, this wasted space can be a noticeable proportion of the die. Since the cost to manufacture a die is directly proportional to the area of the die, it is desirable to make the die as small as possible.
An IO cell tends to be rectangular in shape, and typically in a peripheral IO chip the long side of the IO cells are placed perpendicular to the chip edge and the short side of the IOs are placed parallel to the chip edge. Additionally IO cells are placed all along each edge of the chip to form an IO cell collar, thus a chip will be completely surrounded by IO cells where each IO cell is arranged so that its long axis is perpendicular to the edge of the chip. Accordingly, a footprint of a chip is extended by 2× the length of the IO cells. However, it should be noted that typically the chip only utilizes a fraction of the available IO cells. Thus, a chip will be surrounded by active IO cells, and inactive IO cells. The inactive IO cells consequently take up chip real estate without serving a purpose. But, simply removing the inactive IO cells does not reduce the width or height of the combination of chip and IO cells since there are other IO cells along each side of the chip which are required and thus extend the dimension of the chip along that edge.
The dimensions of a single IO cell in a peripheral IO chip is typically determined by technology limitations and the functionality of the IO cell. When an IO cell is traditionally arranged perpendicular to a chip edge, the short edge of the IO cell dimension is often determined by a combination of the minimum bond pad pitch and the purpose of the IO cell. Next, the long dimension of the IO cell is determined again by the functionality of the IO cell, such as, for example, how much circuitry must fit into the IO cell. Accordingly, the length and width of the IO cell is determined by its functionality, and thus an IO cell has a minimum size beyond which it cannot be reduced. Accordingly, traditional methods of IO cell layout do not consider the design requirements of the IC chip to optimize space, and thus, traditional IO cell layout methods waste space by requiring unnecessarily large IC chip and IO collar designs.
Other conventional methods to configure the IO cells in an IO collar include, rotated IOs, and pad over ESD and pad over active devices. Also included is routing power from power pad to the power bussing w/o the use of an IO power book.